1. Field of the Invention
The present invention relates to a power MOS transistor capable of passing a high level of drain current, which is formed of an array of MOSFET (metal-oxide-semiconductor field effect transistor) cells.
2. Description of the Prior Art
Types of LDMOS FET (lateral diffusion MOSFET, referred to in the following as a LDMOS transistor), formed of an array of interconnected MOSFET cells to constitute a power MOS transistor, are known in the prior art. Such a transistor has a multi-layer configuration of connecting leads, to thereby enable the area occupied by the connecting leads to be reduced and to enable the wiring resistance within the transistor to be lowered. An example of such a prior art LDMOS transistor configuration is shown in FIGS. 20 and 21. As illustrated in the plan view of FIG. 20, this has a conventional stripe configuration of MOSFET cells (source cells and drain cells). The respective source electrodes of the source cells are connected in common to a single connecting lead, which extends to the exterior of the transistor, and the set of gate electrodes and the set of drain electrodes are similarly respectively connected to individual connecting leads, which extend to the exterior of the transistor.
FIG. 21 is a cross-sectional view in elevation of a portion of such a LDMOS transistor, showing the configuration of one of the source cells. As shown in FIG. 21, a contact through-hole (referred to in the following simply as a contact hole) 100 formed in each source cell is large in size, and the source electrode has an N+ source region 101 and a P+ body contact region 102, both of which are at the substrate potential.
With an alternative configuration for such a power MOS transistor, as shown in FIG. 22, the substrate potential and the source potential can be controlled respectively independently. However in that case, it is necessary for the substrate contact area within each source cell to be large in size, so that the area occupied by each source cell becomes large, and hence the overall chip area that is occupied by the LDMOS transistor becomes large.
In addition, although there have been circuits proposed in the prior art for limiting the level of load current which flows in such power MOS transistor, i.e., for overcurrent protection, these have various disadvantages. An example of such a prior art circuit is disclosed in U.S. Pat. No. 4,553,084, and is shown in FIG. 30. Here, a load 200 and a power MOS transistor 201 are connected in series across a power supply voltage, while a sensing transistor 202 and a sensing resistor 203 are connected in series between the drain and source electrodes of the power MOS transistor 201. A gate drive circuit 204 applies a gate drive signal to the gate electrodes of the transistors 201 and 202, so that a form of current mirror relationship exists between the drain currents of these transistors, in the sense that the ratio of the drain currents of transistors 201, 202 is (ideally) always constant, i.e., although that ratio is extremely large, the respective waveforms of these drain currents should be identical, and synchronized with one another.
A voltage whose level represents the level of current flow through the sensing transistor 202 is produced across the sensing resistor 203, and supplied to an amplifier 205. The output from the amplifier 205 can thereby be applied in some manner to prevent excessive current flow through the power MOS transistor 201, e.g., by being supplied to the gate drive circuit 204 such as to cause that circuit to modify the gate drive voltage in a direction which will reduce the level of current flow through the power MOS transistor 201, when the voltage across the sensing resistor 203 exceeds a certain value.
So long as both the power MOS transistor 201 and the sensing transistor 202 are operating with a relatively high value of drain-to-source voltage, with a relatively low level of current flow through the load 200 (i.e., with these transistors each operating in the saturation region of the Id/Vds characteristic, in which the drain current level is unaffected by changes in the drain-to-source voltage), the level of current flow through the sensing resistor 202 will be unaffected by the presence of the sensing resistor 203. In that region of operation, the aforementioned ratio of the drain current through the power MOS transistor 201 to the drain current through the sensing transistor 202 will be accurately maintained. However when the drain-to-source voltage of the sensing transistor 202 becomes low, i.e., when transistors 201, 202 each enter the ON (conducting) state, in which there is an approximately linear relation between the drain-to-source voltage of a FET and its drain current, the current flow through the sensing resistor 202 will be significantly reduced due to the voltage drop across the sensing resistor 203. That is to say, the ratio of the drain current level of transistor 201 to that of the sensing transistor 202 will be substantially increased.
For that reason, it is not possible for such a circuit to be used to perform accurate current limiting of the drain current through the power MOS transistor 201, since the relationship between the respective drain currents of the power MOS transistor and the sensing transistor 202 will vary in accordance with whether these transistors are currently operating in a transition condition between the fully ON and fully OFF states, or are operating in the ON state. Thus, the drain current of the sensing transistor 202 (and hence the voltage developed across the sensing resistor 203) cannot be used to accurately represent the level of load current being passed by the power MOS transistor 201, for the purpose of applying control to limit an excessive level of flow of that load current.
This is an especially serious problem when a power MOS transistor is to be utilized in a form of operation such as PWM (pulse width modulation), in which the transistor is repetitively switched between the ON and OFF states, and so repetitively changes between the transition condition and the fully ON condition, and such limiting to prevent excessive current flow through the power MOS transistor is to be applied, for example as described in Japanese patent No. HEI 9-64707.